An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
نویسندگان
چکیده
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-Encoded Dual-Rail (LEDR) protocol. FPDR protocol is employed to achieve small area for logic blocks, while LEDR protocol is employed to obtain high bit rate and low power for data transfer. Each logic block consists of LEDRFPDR protocol converter, FPDR-LEDR protocol converter and two pipelined FPDR LUTs that alternately operate. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process and the simulation result shows that the throughput is 3.91 GHz.
منابع مشابه
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters...
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